The technology described herein relates to graphics processing methods and systems in which graphics data stored in memory is accessible using virtual memory addresses that map to physical memory addresses in the memory.
In order to access graphics data stored in memory, many graphics processing systems use virtual memory addressing arrangements. In these arrangements, the address used in a given memory access request is translated from a virtual memory address used by the unit requesting the memory access to a corresponding physical memory address in memory. To perform the translation between the virtual memory address used for a memory access request and the corresponding physical memory address where the graphics data is actually stored, a set of address translation data, which maps virtual memory addresses used in memory access requests to corresponding physical memory addresses, is usually stored.
Memory accesses are typically performed in a memory management unit (MMU) of the graphics processing system. The MMU usually allocates the physical memory for graphics data storage in given units of memory size, typically referred to as “pages”, and associates corresponding virtual memory addresses for the pages with the physical memory addresses where the page of graphics data is actually stored in memory. Thus, the memory address translation data is typically provided by an MMU and is usually in the form of a so-called “page table”.
As will be appreciated, using virtual memory addresses provides a level of abstraction that can, for example, allow different units of the graphics processing system to access the graphics data stored in a shared main memory using their own sets of virtual addresses whilst allowing the MMU to maintain the integrity (e.g. prevent inadvertent overwrites or deletions) of the graphics data that is stored at the physical memory addresses of the memory.
The Applicants believe that there remains scope for improvements to graphics processing methods and systems in which graphics data stored in memory is accessible using virtual memory addresses that map to physical memory addresses in the memory. For example, in graphics processing systems, e.g. of portable devices, it is generally desirable to try to reduce the amount of memory required to store sets of graphics data and/or to try to increase efficiency, e.g. so as to reduce power consumption and/or increase processing speed, but without a corresponding undesirable reduction in the quality or resolution of the graphics data.
The drawings show elements of a graphics processing system that are relevant to embodiments of the technology described herein. As will be appreciated by those skilled in the art there may be other elements of the graphics processing system that are not illustrated in the drawings. It should also be noted here that the drawings are only schematic, and that, for example, in practice the shown elements may share significant hardware circuits, even though they are shown schematically as separate elements in the drawings.